Volatile circuits have been and are the norm in digital technology. In order to maintain information, continuous power is necessary. Accordingly, in order to minimize the power consumed when there is no user activity, digital technologies, including custom and ASIC, applications typically feature some form of standby, sleep or low power mode in contrast to the normal or run mode. The standby or sleep mode exhibits greatly reduced power dissipation. Standby mode or sleep mode may be defined by interruption of the system clock or by disconnecting the power supply or by both. Power is most effectively minimized when all, or almost all, of the logic on a chip can be disconnected from the power supply. Modern logic technologies tend to be optimized for performance, and as a result the "off" currents of logic transistors can be substantial. This, of course, minimizes the advantages which might be gained from any sleep or standby mode in which power remains continuously applied.
Recovery from the standby mode in which power is interrupted usually requires returning the chip to the state it was in just prior to entering the standby mode. Typically this requires saving the state of the latches. In some systems, there may be provision for an elaborate powerdown sequence in which the content of latches and registers can be stored on a hard disk. Simple applications, on the other hand, cannot justify a hard disk for these features. In addition, the complexity of the power-down sequence may be undesirable. The present invention is directed at providing a simple and inexpensive solution which implements a power-down standby mode in an efficient and effective manner The simplicity and efficiency of the invention recommend it for use on devices as simple as a pocket calculator, as well as in more complex devices.